The present disclosure relates generally an integrated circuit (IC) device and, more particularly, to method for forming a complementary metal oxide semiconductor (CMOS) structure.
As technology nodes shrink, in some IC designs, there has been a desire to incorporate strained engineering, including SiGe, SiC, SiP and/or Si epitaxial (epi) process, in the formation process of CMOS devices to overcome Moore's law.
There are challenges to implement such epi features and processes in CMOS fabrication. As technology nodes continue to decrease, particularly to 22 nm technology node and below, the formation selectivity between a pre-determined region designed for the formation of the epi film and a protective layer not suitable for the formation of the epi, polycrystalline, or amorphous film thereon during an epi formation process is a key challenge for forming the epi film. A low formation selectivity means that there is no significant difference between a growth rate of an epi film formed on the pre-determined region and a growth rate of an epi, polycrystalline, or amorphous film formed on the protective layer. It may subsequently cause epi loss on the pre-determined region when removing the unwanted epi, polycrystalline, or amorphous film on the protective layer, and thereafter resulting defects in CMOS device and impact the yield of device. Alternatively, tuning a low epi formation rate may be helpful for increasing the epi formation selectivity between different regions. However, the decreased epi formation rate decreases the throughput of IC production.